1. Field of the Invention
The present invention generally relates to image processing, and more particularly to hierarchical motion estimation.
2. Description of Related Art
In performing motion estimation to generate motion vectors, pixel data of a reference frame such as a previous frame are required to be retrieved from an external memory device. Considering the limited bandwidth of the memory device, it is almost inconceivable that pixel data could be retrieved from a usual memory device such as DDR SDRAM (double data rate synchronous dynamic random access memory) in a real-time manner.
In order to alleviate this difficulty, an internal memory area such as that of a cache is reserved in an integrated circuit for temporarily storing a portion, such as a search range, of the reference frame. Unfortunately, the size of the internal memory area becomes unacceptable for high-definition (HD) video with resolution of, for example, 1920×1080 pixels. As an example, for the search range of 1/10 in the HD video, the memory size of 108 (i.e., 1080*( 1/10)) scan lines or, equivalently, 1658880 (i.e., 108*1920*8) bits, is required.
For the reason that conventional motion estimation systems or methods could not be practically adapted to higher-resolution video, a need has arisen to propose a novel scheme that is adaptable to higher-resolution video such as HD video in a practical manner.